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July 30, 20268 min readInstead of compromising among parameter updates dictated by different training objectives, ControlG allocates computational capacity to objectives sequentially and dynamically.
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July 9, 202610 min read
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Featured news
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IEEE ITherm 20222022Portable consumer electronics devices continue to be one of electronics high-demand items, with rising interest in such products recently. Li-Ion batteries are the most popular power source choice of these products owing to a combination of high specific energy and specific power. In consumer electronics products, these batteries are generally employed in their coin form factor in biomedical devices, sensors
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VLDB 20222022Content delivery networks (CDNs) are critical for minimizing access latency in the Web as they efficiently distribute online resources across the globe. But since CDNs can only be enabled on the scope of entire websites (and not for individual users or user groups), the effects of page speed acceleration are often quantified with potentially skewed before-after comparisons rather than statistically sound
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ICLR 2022 Workshop on Deep Generative Models for Highly Structured Data2022Performance of recommender systems (RecSys) relies heavily on the amount of training data available. This poses a chicken-and-egg problem for early-stage products, whose amount of data, in turn, relies on the performance of their RecSys. In this paper, we explore the possibility of zero-shot learning in RecSys, to enable generalization from an old dataset to an entirely new dataset. We develop, to the best
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SIGIR 20222022Many IR collections contain forbidden documents (𝐹 -docs), i.e. documents that should not be retrieved to the searcher. In an ideal scenario 𝐹 -docs are clearly flagged, hence the ranker can filter them out, guaranteeing that no 𝐹 -doc will be exposed. However, in real-world scenarios, filtering algorithms are prone to errors. Therefore, an IR evaluation system should also measure filtering quality in
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DesignCon 20222022Electrostatic discharge (ESD) events can result in soft and hard failures to an integrated circuit (IC). To protect the ICs from ESD, ESD protection structure is critical for chip-level design. Since chip-level internal ESD protection circuit information is often not released to the public, we propose a new modeling methodology using vector network analyzer (VNA), time domain reflectometer (TDR), source
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