On-chip ESD protection structure modeling methodology
Electrostatic discharge (ESD) events can result in soft and hard failures to an integrated circuit (IC). To protect the ICs from ESD, ESD protection structure is critical for chip-level design. Since chip-level internal ESD protection circuit information is often not released to the public, we propose a new modeling methodology using vector network analyzer (VNA), time domain reflectometer (TDR), source meter unit (SMU), and three terminal transmission line pulse (TLP) test, for the first time, to accurately obtain both quasi-static current-voltage (IV)-curves and small signal model of the on-chip ESD protection structure based on the published single Transient Voltage Suppressor (TVS) modeling framework. Besides, the transient waveform characterization using very fast TLP (VF-TLP) for discrete on-chip ESD protection structure is investigated and an improved modeling methodology is proposed. Our proposed measurement-based IC ESD protection modeling is verified by simulation and measurement results on multiple ICs. Our proposed model can be further used in optimizing the system-level ESD protection without information on internal IC ESD protection scheme.